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 Dual Synchronous Voltage Mode Controller with Current Sharing Circuitry
POWER MANAGEMENT Description
The SC2677B is a versatile 2 phase, synchronous, voltage mode PWM controller that can be used in two distinct ways. First, the SC2677B is ideal for applications where point of use output power exceeds any single input power budget. Alternatively, the SC2677B can be configured as a dual switcher. The SC2677B features a precise temperature compensated voltage reference, cycle-by-cycle peak current limit, under voltage lockout over current protection, and internal level-shifted high-side gate drive circuitry. In current sharing configuration, the SC2677B can produce a single output voltage from two separate input voltage sources (which can be different in voltage levels) while maintaining current sharing between the two channels. Current sharing is programmable to allow each input supply to be loaded differently per application requirements. In dual switcher configuration, two feedback paths are provided for independent control of the separate outputs. The device will provide a regulated output from flexibly configured inputs, such as 3.3V, 5V, 12V etc. The phasing between the two switchers is adjustable to minimize the input and output ripple.
SC2677B
Features
300kHz to 1MHz externally programmable frequency operation Soft Start and Enable function Power Good output provided Cycle-by-cycle peak current limit Latch Off for over current protection Phase-shifted switchers minimize ripple High-efficiency operation, >90% Programmable output(s) as low as 0.5V Industrial temperature range TSSOP-24 package TSSOP-24 EDP package Bias voltage as low as 4.5V Adjustable phase shift between channels Two Phase, Current Sharing Controller Flexible, same or separate VIN Programmable current sharing Thermal distribution via multi-phase output
Applications
Graphics cards Peripheral add-in card Dual-phase power supply Power supplies requiring two outputs
CS1CS1+ C63 R51
Typical Application Schematic
D2
D1
C6 R50 M1 C4 M3 L1 1 2
Vout1
R5
C19 C23 R8
PW RGD
ENABLE
CS1+ CS1C28 R13 C26 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 C25 R14 R10 PS HA ING
P RG WD
S /E S NA
C1 S+
G ND
CO P M1
Vin
R19
U1
FRE Q VF RE C2 S+ C2 S-
SC2677B
CO P M2 P ND G B T2 S + IN2 V CC DH2 -IN2 D2 L C33
1 0
1 1
1 2
1
2
3
4
5
6
7
8
9
B TC S
B T1 S
-IN1
DH1
C1 S-
D1 L
R21 CS2+ CS2C36
R20
CS2C39 C38 CS2+
R49 C62 R18
R48 L2 1 M5 C43 D3 D4 C59 M7 C57 2
Vout2
Dual Independent outputs
Revision: Dec. 15, 2004
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SC2677B
POWER MANAGEMENT Typical Application Schematic
D2
Vin3
CS1R51 CS1+ C63 D1 C6 R50 M1 C4 M3 R5 C23 C19 R8 L1 1 2
Vin1
VP1
Vout
PW RGD ENABLE
CS1+ CS1C28 R13 C26 24 23 22 21 20 19 18 17 16 15 14 13 C25 R14 R10 P A IN HS G S /E A SN
C 1+ S
C M1 OP
B T1 S
-IN 1
D1 H
P RD WG
GD N
D L1
C M2 OP
R19
U1
FR Q E VE RF C 2+ S C 2S
SC2677B
P ND G B T2 S +2 IN VC C D2 H -IN 2 D2 L C33
10
11
12
1
2
3
4
5
6
7
8
9
B TC S
C 1S
R21
CS2+ CS2C36 C37 VOUT R22 C35 VOUT
Vin3
R24 C39 C38 VP1
R26
VP2 CS2CS2+ C62 R48 L2 1 2
R49
D
Vin2
M5 C43 D3 D4 C59
VP2
M7
C57
Vin3
Dual Input, Single Output, Current Share Mode
D2 CS1R51 CS1+ C63 D1 C6 R50 M1 C4 M3 R5 C19 C23 R8 L1 1 2
VP1
Vout
PW RGD
ENABLE
CS1+ CS1C28 R13 C26 24 23 22 21 20 19 18 17 16 15 14 13 C25 R14 R10
P HAS ING
PW D RG
S NA S/E
CS1+
G ND
CO 1 MP
Vin
R19
U1
FRE Q VRE F CS2+ CS2-
SC2677B
CO MP2 PG ND BST2 VCC +IN2 DH2 -IN2 DL2 C33
10
11
12
1
2
3
4
5
6
7
8
9
BS TC
B ST1
-IN1
DH1
CS1-
DL1
R21
CS2+ CS2C36 C37 VOUT R22 C35 VOUT
R26 R24 C39 C38 VP1 CS2CS2+
VP2
R49 C62 R48 L2 1 2
D
VP2
M5 C43 D3 D4 C59 M7
C57
Single Input/Output, Current Share Mode
(c) 2004 Semtech Corp.
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SC2677B
POWER MANAGEMENT Absolute Maximum Rating
Exceeding the specifications below may result in device malfunction or permanent damage to the device. Operation beyond the parameters specified in the "Electrical Characteristics" section is not recommended.
P ar am et er V CC to GN D PGN D to GN D BST1, BST2 to GN D BSTC to GN D -IN 1, +/-IN 2 to GN D COMP1, COMP2 to GN D DH1, DH2 to GN D DL1, DL2 to GN D
(6)
S y m b ol V IN
Li mi ts -0.3 to 15 1 -0.3 to 30 -0.3 to 20 7 7 -0.3 to 30 -0.3 to BSTC + 0.3 -3 p eak (50nS)
(1)
Units V V V V V V V V V V V V V C/W
CS1+, CS1-, CS2+, CS2PWRGD to GN D PHA SIN G SS/EN A to GN D Thermal Resistance Junction to Case TSSOP-24 TSSOP-24 EDP Thermal Resistance Junction to A mb ient TSSOP-24 TSSOP-24 EDP Op erating A mb ient Temp erature Range Op erating Junction Temp erature Range Storage Temp erature Range Lead Temp erature (Sold ering) 10 sec JC
7 V CC + 0.3 7 -0.3 to 7 17 5.5 90 32 -40 to 85 -40 to 125 -65 to +150 300
JA TA TJ TSTG T LE A D
C/W C C C C
Electrical Characteristics
Unless Specified: VCC = 4.75 to 5.25V, GND = PGND = 0V, FB = VO, TJ = 25C, VBSTC = VBST = 12V
P ar am et er Outp ut Voltage Con d i t i on s V OUT = V FB V OUT = V FB, -40 to 125 C
o
Min 0.495 0.492 4.5
Ty p 0.500 0.500
M ax 0.505 0.508 15
Units V V V mA V mV V
Sup p ly Voltage Sup p ly Current U V LO UV LO Hy steresis Reference Reference Load Regulation Reference Line Regulation Outp ut Line Regulation Gain (Gm) (Error A mp lifier) Inp ut Offset Voltage (Slave Error A mp lifier) Max Current (Error A mp lifier) Inp ut Bias Current
V CC V CC = 5.0 V CC Ramp up Th resh old V CC
10 2.84 100 0.5
V REF source 10uA ~ 100uA 5V < V CC < 15V 5V < V IN < 15V COMP p in source 100uA 4 -3 Source, Sink -IN 1, +IN 2, -IN 2 400 5 -1 460
0.2 0.7 0.7 6 0
% % % mA /V mV A
2
A
(c) 2004 Semtech Corp.
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SC2677B
POWER MANAGEMENT Electrical Characteristics (Cont.)
Unless Specified: VCC = 4.75 to 5.25V, GND = PGND = 0V, FB = VO, TJ = 25C, VBSTC = VBST = 12V
P ar am et er Und er Voltage Latching off Threshold Oscillator Freq uency Range Oscillator Freq uency Oscillator Max Duty Cycle Phasing of DH2 and DH1 DH Sink Current DH Sink Current DH Source Current DH Source Current DL Sink Current DL Sink Current DL Source Current DL Source Current DH Minimum on Time Dead Time Soft Star t Charge Current Soft Star t Enab le Soft Star t End Soft Star t Transition Threshold OCP Trip Threshold OCP Delay Time Inp ut Offset (Current Sense A mp lifier) Inp ut Bias Current Pow er Good Threshold Pow er Good Pull Dow n CS1+, CS1-, CS2+, CS2V OUT ramp ing up Sink Current = 2mA 83% 88% From OCP d etection to DH low +/-3 100 93% 0.4
(2) (2)
Con d i t i on s
Min 60 300
Ty p 70
M ax 80 1000
Units % kHz kHz % A A A A A A A A
RSET = 5kohm FOSC = 500kHz V PHASING = 0.585V DH - PGN D = 3.5V DH - PGN D = 2.5V BSTH - DH = 3.75V BSTH - DH = 3V DL - PGN G = 3.5V DL - PGN D = 2.5V BSTL - DL = 3.75V BSTL - DL = 3V -40 to 0 C
o
450 86
500 90 180
550
1.7 0.85 1.7 0.85 1.7 0.85 1.7 0.85 300 50 85 50 120
ns ns A mV mV V 37 200 mV nS mV nA V OUT V
N ote 5
0% d uty cycle 100% d uty cycle Synchronous mod e 28
400 825 1.22 33
Notes: (1) Measured from 50% to 50% pulse amplitude. (2) The Soft Start pin sources 50A to an external capacitor. The converter operates in synchronous mode above the Soft Start transition threshold and in asynchronous mode below it. (4) This device is ESD sensitive. Use of standard ESD handling precautions is required. (5) 120ns maximum at 70C. (6) Under pulsing condition, the negative voltage can be -5V for no more than 40ns measured from 50% falling to 50% rising.
(c) 2004 Semtech Corp.
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SC2677B
POWER MANAGEMENT Pin Configuration
Top View
Ordering Information
D e v i c e ( 1) SC2677BITSTRT
( 2)
P ack ag e TSSOP-24 TSSOP-24 EDP Current Share Evaluation Board Dual Channel Evaluation Board
SC2677BTETRT( 2) SC2677BEV B-1 SC2677BEV B-2
Notes: (1) Only available in tape and reel packaging. A reel contains 2500 devices. (2) Lead free package. Device is fully WEEE and RoHS compliant.
(TSSOP-24 Pin)
Pin Descriptions
EXPANDED EXP ANDED PIN DESCRIPTION 1, 24: Pin 1 , 24: (CS2+, CS1+) Current sense amplifier (for OCP protection) non-inverting inputs. Pin 2, 23: (CS2-, CS1-) Current-Sense Amplifier (for OCP protection) inverting inputs. Pin 3: (VREF) Internal 0.5V reference. Connected to the "+" input of the Master Channel Error Amplifier. Pin 4: (FREQ) External frequency adjustment. Connect a resistor to AGND to set the switching frequency. Please see more information in "Application" section. Pin 5: (VCC) Bias pin for the controller. Connect a ceramic decoupling capacitor from this pin to AGND with minimum trace length. Pin 6: (+IN2) "+" input of the slave error amplifier. Pin 7, 18: (-IN2, -IN1) "-" inputs of the Error Amplifiers. 17 Pin 8, 17: (COMP2, COMP1) Compensation pins of the Error Amplifiers. 16: Pin 9, 16: (BST2, BST1) Supply pins for the high side drivers. Usually connected to bootstrap circuit. Pin 10, 15: (DH2, DH1) Gate drive pins for the top MOSFETs. Requires a small series resistor. Pin 11, 14: (DL2, DL1) Gate drive pins for the bottom MOSFETs. Requires a small series resistor. Pin 12: (PGND) Power GND. Return of the high side and low side gate drivers. Pin 13: (BSTC) Supply pin for bottom MOSFET gate drivers. Pin 19: (PHASING) This pin controls the phase shift between Master and Slave for optimum noise immunity. Use a resistive divider from the FREQ pin (pin 2) to AGND, and connect the tap of the resistive divider to pin 17. Please see more information in "Application" section. Pin 20: (SS/ENA) Soft Start pin. Connect a ceramic capacitor from this pin to AGND, and there is an internal current source charging up this capacitor during Soft Start. The PWM operation can be disabled if this pin is pulled low. 21: Pin 21: (PWRGD) Power Good signal. This is an open collector output. It is pulled low internally if output voltage is outside the Power Good window. Pin 22: (GND) Analog GND. Return of the analog signals and bias of the chip.
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(c) 2004 Semtech Corp.
SC2677B
POWER MANAGEMENT Block Diagram
1.25V 50uA
Notes: (1) Channel 1 is the Master and Channel 2 is the Slave in current sharing configuration. (2) For dual output operation, tie +IN2 to VREF will make the two PWM independent.
(c) 2004 Semtech Corp.
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SC2677B
POWER MANAGEMENT Application Information
Main Loop(s) The SC2677B is a dual-voltage mode synchronous Buck controller. The two separate channels are identical and share only IC supply pins (Vcc and GND), output driver ground (PGND) and pre-driver supply voltage (BSTC). They also share a common oscillator generating a sawtooth waveform for Channel 1 and an dephased sawtooth for Channel 2. Both Error Amplifier inputs on Channel 2 inputs are uncommitted and available externally. This allows the SC2677B to operate in two distinct modes. a) Two independent channels with either common or different input voltages and different output voltages. The two channels each have their own voltage feedback path from their own output. In this mode, positive input of the Error Amplifier 2 is connected externally to Vref. If the application uses a common input voltage, the sawtooth phase shift between the channels provides some measure of input ripple current cancellation. b) Two channels operating in current sharing mode with common output voltage and either common input voltage or different input voltages. In this mode, Channel 1 operates as a voltage mode Buck controller, as before, but Error Amplifier 2 monitors and amplifies the difference in voltage across the output current sense resistors of Channel 1 and Channel 2 (Master and Slave) and adjusts the Slave duty cycle to match output currents. To controller also works well for using the output choke winding resistance as current sensing element (please refer the "Application" schematic for details). The amount of the current of the Slave Channel vs. the Master Channel can be programmed according to the application. This feature is especially useful when two input sources are used and each source has its own power budget. The offset of the current sharing Error Amplifier is trimmed within the range of -2mV to 0mV. The Slave is OFF if the Master has no current. Power Good The controller provides a Power Good signal. This is an open-collector output, which is pulled low if the output voltage is outside the Power Good window. Soft Start/Enable The Soft Start/Enable (SS/ENA) pin serves several functions. If held below the Enable threshold, both channels are inhibited. DH1 and DH2 will be low, turning off the top FETs. Between the Soft Start Enable threshold and the Soft Start End threshold, the duty cycle is allowed to increase. At the Soft Start End threshold, maximum duty cycle is reached. In practical applications, the Error Amplifier will control the duty cycle before the Soft Start End threshold is reached. To avoid boost problems during startup in current share mode, both channels start up in asynchronous mode, and the bottom FET body diode is circulates current during the top FET off time. When the SS/ENA pin reaches the Soft Start Transition threshold, the channels begin operating in synchronous mode for improved efficiency. The Soft Start pin sources approximately 50uA, and Soft Start timing can be set by selection of an appropriate Soft Start capacitor value. requency Set F req uency Se t and Phasing The switching frequency can be programmed by connecting a resistor from the FREQ pin to AGND. The PHASING pin controls the phase shift between the Master sawtooth and Slave sawtooth which allows the adjustment of the phase shift for maximum noise immunity by controlling the timing between Master and Slave transition. A resistive divider is used from the FREQ pin to AGND and the divided voltage is fed to the PHASING pin as depicted.
R13 24 23 22 21 20 19 18 17 16 15 14 DL1 11 DL2 13 12 PGND BSTC
CS1+
PHASING
SS/ENA
COMP1
BST1 BST2 9
-IN1
CS1-
U1
PWRGD
GND
R19
SC2677B
COMP2 FREQ VREF CS2+ CS2+IN2 VCC DH2 10 -IN2
1
2
3
4
5
6
7
(c) 2004 Semtech Corp.
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DH1
SC2677B
POWER MANAGEMENT Application Information(Cont.)
(R13+R19) vs.Oscillator Frequency 1000 Oscillator Frequency (kHz) 900 800 700 600 500 400 300 4 6 8 10 12 14 16 18 20 (R13+R19) (kohm)
ICC QGT QG FSW N
: Supply current for controller. : Total gate charge of all selected MOSFETs. : Total gate charge of per selected MOSFETs. : Switching frequency. : Number of MOSFET.
It is recommended that the below figure be studied to ensure SC2677B is used under safe operating conditions.
QGT limitation (with loading) 620 580 540 500 460 420 380 340 300 260 220 180 140 100 60 20 150
Vphasing vs Phase Shift
SOA
5Vin 8.5Vin 12Vin
180 160 140 Phase (deg) 120 100 80 60 40 20 0 0.55 0.60 0.65 0.70 0.75 0.80 0.85 0.90
QG T(n C )
SOA
SOA
200 250 300 350 400 450 500
Vphasing (V)
Fsw(KHz)
OverCurrent Protection Current-sense amplifiers sense the inductor DCR, and compare with an internal OCP reference. When overcurrent is detected, the current-sense amplifier will trip the peak current limit on cycle-by-cycle basis. If the overcurrent condition sustains, and the output voltage drops below 75% of its nominal voltage level, the PWM will be disabled and the power supply will be latched off with a short amount of delay. The latch can be reset by power cycling. Controller Power Dissipation Controller power dissipation is generated by the following parameter; switching frequency, total gate charge of all selected MOSFETs and supply voltage. P = Vin * (ICC + QGT* FSW) QGT = QG * N Where Vin : Supply voltage for controller and driving MOSFET.
(c) 2004 Semtech Corp.
This example demonstrates the procedure introduced above. Vin =12V Fsw =250KHz N =4(number of MOSFET) Then QGT = 108nC QG = 27nC (per MOSFET) Layout Guidelines Power and signal traces must be kept separate for noise considerations. Feedback, current-sense traces and analog ground should not cross any traces or planes carrying high-switching currents, such as in the input loop or the phase node. The input loop, consisting of the input capacitors and both MOSFETs must be kept as small as possible. Since all of the high switching currents occur in the input loop, the enclosed loop area must be kept small to minimize inductance and radiated and conducted noise emissions.
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SC2677B
POWER MANAGEMENT Application Information (Cont.)
Designing for minimum trace length is not the only factor for best design. Often, a optimum layout can be achieved by keeping the wide trace and using proper layer stacking to minimize the stray inductance. It is important to keep the gate traces short. The IC must be close to the power switches. It is recommended that a 25 mil width or wider trace is used whenever possible. A good placement can help if the controller is placed in the middle of the two PWM channels. Grounding requirements are always important in a Buck converter layout, especially at high power. Power ground (PGND) should be returned to the bottom MOSFET source to provide the best gate current return path. Analog ground(AGND) should be used for the analog returns such as chip decoupling, frequency setting, reference voltage (or Soft Starting cap), and the compensation. This ground shape should be single-point connected to the PGND shape near the ground side of the output capacitors. This will provide noise-free analog ground for operation stability, and also provide the best possible remote sensing for the feedback voltage. In case two output rails need to be regulated, the AGND shape should be single-point connected to the geometrical center of the PGND for the two point of loads. The single-point tie is a must to prevent the power current from flowing on the AGND shape, so that the analog circuitry in the controller has an electrically quiet reference, and to provide the greatest noise-free operation. Keep in mind that the AGND pin is never allowed to have bigger than 1V voltage difference vs the PGND pin. This is usually achievable by using a ground plane for PGND in PCB layout. Using ground plane for PGND can reduce the physical separation between the two grounds so that even the fast current transitions in the PGND plane cannot generate voltage spikes exceeding the 1V level. This will prevent unstable and erratic behavior. The feedback divider must be close to the IC and be returned to analog ground. Current sense traces must be run parallel and close to each other and to analog ground. The IC must have a ceramic decoupling capacitor across its supply pins, mounted as close to the device as possible. The small ceramic noise-filtering capacitors on the current-sense lines should also be placed as close to the IC as possible.
(c) 2004 Semtech Corp.
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SC2677B
POWER MANAGEMENT Evaluation Schematic
Dual Independent Outputs
CS1CS1+
R51 13K C63 220nF L1 8.8uH
M1
VP1
+12V
IPD13N03LA
R50 7.32K
Vout1 5V@2A
C10 C19 1800uF
DCR=8.83mohm
C6 C1 4.7uF C4 1000uF D1 D1N4148 D2 D1N4148 C23 R5 7.5K C24 1uF R8 9.09K C25 1uF 1uF M3 IP D13N03LA R1 1.0 C21 1nF C9
4.7uF 4.7uF
PWRGD
R9 10.0K R11 10.0K Q1 2N3904 Q2 2N3904 R12 300 C28 0.1uF
CS1CS1+
1uF
R13 4.42k
C26 C27 O ption 100nF R14 12.4K
R10 1.00K
Enable
R19 6.19K
U1
C S2+ C S1+ C S2C S1VREF G ND PW R G D F REQ VCC SS/ENA +IN2 PH ASING -IN2 -IN1 C O MP2 C O MP1 B ST 2 B ST1 D H2 D H1 D L2 D L1 PG N D BSTC
SC2677B
Enable/Disable Circuit(option)
24 23 22 21 20 19 18 17 16 15 14 13
C33 C34 47pF 47nF R21 4.53K R18 5.6K
1 2 3 4 5 6 7 8 9 10 11 12
Delay Output Circuit(option)
C40 4.7uF
C S2 C S2 +
C36 0.1uF R31 2.2 C38 1uF C39 1uF M5 IPD13N03LA C59 1uF
+12V
R20 2N3906 1K R54 3K D5
Q3
R52 2K
1N4148 R55 4.7k C50 1uF
R53 8K
CS2CS2+
R49 33.2K C62 R48 4.02K 220nF L2
S_ E n a b le
VP2
Vout2 3.3V@2A
DCR=6.35mohm
M7 IP D13N03LA R35 1.0 C47 C60 1nF 4.7uF C46 4.7uF C57 1800uF
4.7uH
C43 1000uF
D3 1N4148
R36 0R0
D4 1N4148
(c) 2004 Semtech Corp.
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SC2677B
POWER MANAGEMENT Evaluation Board - Bill of materials
Dual Independent Outputs
Item 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 Referen ce C1,C9,C10,C40,C46,C47 C4,C43 C19,C57 C6,C23,C25,C28,C38,C39,C59,C50 C21,C60 C24,C36 C26 C33 C34 C62,C63 L1 L2 M1,M3,M5,M7 D1,D2,D3,D4,D5 Q1,Q2 Q3 R1,R35 R5 R8 R9,R11 R10 R12 R13 R14 R18 R19 R20 R21 R31 R36 R48 R49 R50 R51 R52 R53 R54 R55 U1 Qu an ti ty 6 2 2 8 2 2 1 1 1 2 1 1 4 5 2 1 2 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Descri p ti on 16V Cerami c Cap , X7R 16V A l u mi n u m El ectrol y ti c Cap . 16V A l u mi n u m El ectrol y ti c Cap . 16V Cerami c Cap , X7R 16V Cerami c Cap , X7R 16V Cerami c Cap , X7R 16V Cerami c Cap , X7R 16V Cerami c Cap , X7R 16V Cerami c Cap , X7R 16V Cerami c Cap , X7R In d u ctor In d u ctor 30V N -Ch an n el MOSFET Smal l Si gn al Di od e N PN Gen eral Pu rp ose A mp l i fi er PN P Gen eral Pu rp ose A mp l i fi er SM 5% SM 5% SM 5% SM 5% SM 5% SM 5% SM 5% SM 5% SM 5% SM 5% SM 5% SM 5% SM 5% SM 5% SM 5% SM 5% SM 5% SM 5% SM 5% SM 5% SM 5% SM 5% PWM con trol l er Par t 4.7u F 1000u F/16V 1800u F/16V 1u F 1n F 0.1u F 100n F 47n F 47p F 220n F 8.8u H/4m oh m 4.7u H/4m oh m IPD13N 03LA 1N 4148 2N 3904 2N 3906 1oh m 7 5K . 9.09K 10K 1K 300oh m 4.42K 12.4K 5.6K 6.19K 1K 4.53K 2.2oh m 0oh m 4.02K 33.2K 7 32K . 13K 2K 8K 3K 4.7K SC2677B
(c) 2004 Semtech Corp.
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SC2677B
POWER MANAGEMENT Performance (Dual Output)
Test condition:12Vin,5Vout@0A, 3.3Vout@0A Vcc 5Vout 3.3Vout PWRGD
Test condition:12Vin,5Vout@short circuit, 3.3Vout@ 0A Vcc
5Vout 3.3Vout
PWRGD
Test condition:12Vin,5Vout@2A, 3.3Vout@2A
Test condition:12Vin,5Vout@2A,3.3Vout@short Vcc
Vcc 5Vout
5Vout
3.3Vout
3.3Vout PWRGD
PWRGD
Test condition:12Vin,5Vout@2A, 3.3Vout@2A
DH1 DL1
DH2 DL2
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SC2677B
POWER MANAGEMENT Performance (Dual Output)
5V OCP
3.3V O CP
6.0 5.0
3.0 2.0 1.0 0.0 0 1 2 3 4 5 6 7 Load Current (A)
Vout2 (V)
Vout1 (V)
4.0
3.6 3.2 2.8 2.4 2.0 1.6 1.2 0.8 0.4 0.0 0 1 2 3 4 Load C urrent (A ) 5 6
Load Current vs. Vcs1+ to Vout1
Load Current vs.Vcs2+ to Vout2
40 Vcs1+ to Vout1 (mV) 30 25 20 15 10 5 0 0 1 2 3 4 5 Load Current (A) 6 7
Vcs2+ to Vout2 (mV)
40 35 30 25 20 15 10 5 0 0 1 2 3 4 Load Current (A) 5 6
35
Ove ra ll S yste m Efficie ncy 96 94 92
Efficiency (%)
90 88 86 84 82 80
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 Io1+Io2
Loa ding (A)
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SC2677B
POWER MANAGEMENT Evaluation Schematic (Cont.)
Single Output, Current Share Mode
(1)
CS1CS1+
R51 5.76K C63 220nF L1 2uH
+3.3V
M1 IPD09N03LA
VP1
R50 6.34K
Vout1 1.4V@20A
C9 4.7uF C10 4.7uF C19 1800uF C20 1800uF
DCR=4mohm
C6 C1 4.7uF C4 1800uF D1N4148 D1N4148 D1 D2 IPD06N03LA 1uF M3 R1 1.0 C21 1nF
+12V
C23 R5 7.5K C24 1uF R8 1.78K
PWRGD
R9 10.0K R11 10.0K Q1 2N3904 Q2 2N3904 R12 300 C28 0.1uF
C25 1uF
CS1+
CS1-
1uF
R13 4.64k
C26 47nF
R10 1.00K
Enable
24
23
22
21
20
19
18
17
16
15
14
13
R14 8.06K
CS1+
CS1-
PWRGD
SS/ENA
GND
COMP1
Enable/Disable Circuit (option)
R19 5.9K U1
COMP2
SC2677B
PHASING
BSTC
-IN1
BST1
DH1
DL1
PGND
FREQ
VREF
BST2
CS2+
C33 33nF R21 2.1K
CS2-
+IN2
VCC
DH2 10
-IN2
11
DL2
12
1
2
3
4
5
6
7
8
9
R31 1N4148 2.2 C39 1uF
CS2+
C36 0.1uF C38 1uF
CS2R24 4.87K C37 220nF R26 4.3K
R22 2.32K
VP2
VP1
C35 220nF
Vout Vout
D5
CS2CS2+
(1)
C62 220nF
M5
VP2
R48 3K L2
+5V
IPD09N03LA C59 1uF M7 IPD06N03LA C60 1nF R35 1.0
DCR=4mohm
2uH
C40 4.7uF
C43 1800uF
D3 1N4148
C47 4.7uF
C46 4.7uF
C56 1800uF
C57 1800uF R36 0R0
D4
+12V
1N4148
Note (1) : Current Scale. Master channel current w eighting factor is around 0.68 * Io, Slaver is around 0.32 * Io
(c) 2004 Semtech Corp.
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SC2677B
POWER MANAGEMENT Evaluation Board - Bill of Materials
Single Output, Current Share Mode
Item 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Reference C1,C9,C10,C40,C46,C47 C4,C19,C20,C43,C56,C57 C6,C23,C25,C28,C38,C39,C59 C24,C36 C26 C33 C35,C37,C62,C63 L1,L2 M1,M5 M3,M7 D1,D2,D3,D4,D5 Q1,Q2 R1,R35 R5 R8 R9,R11 R10 R12 R13 R14 R19 R21 R22 R24 R26 R31 R36 R48 R50 R51 U1 Quanti ty 6 6 7 2 1 1 4 2 2 2 5 2 2 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Descri p ti on 16V Cerami c Cap , X7R 16V A lumi num Electroly ti c Cap . 16V Cerami c Cap , X7R 16V Cerami c Cap , X7R 16V Cerami c Cap , X7R 16V Cerami c Cap , X7R 16V Cerami c Cap , X7R Ind uctor 25V N -Ch annel MOSFET 25V N -Ch annel MOSFET Small Si gnal Di od e N PN General Purp ose A mp li fi er SM 5% SM 5% SM 5% SM 5% SM 5% SM 5% SM 5% SM 5% SM 5% SM 5% SM 5% SM 5% SM 5% SM 5% SM 5% SM 5% SM 5% SM 5% PWM controller Par t 4.7uF 1800uF/16V 1uF 0.1uF 47nF 33nF 220nF 2uH/4m oh m IPD09N 03LA IPD06N 03LA 1N 4148 2N 3904 1oh m 7 5K . 1.78K 10K 1K 300oh m 4.64K 8.06K 5.9K 2.1K 2.32K 4.87K 4.3K 2.2oh m 0oh m 3K 6.34K 5.76K SC2677B
(c) 2004 Semtech Corp.
15
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SC2677B
POWER MANAGEMENT Performance (Single Output)
Test condition: 3.3Vin/5Vin, Io=0A
Test condition: 3.3Vin/5Vin, Io=20A
Vout
Vout
SS/EN DH1 DL1
Io
PWRGD
Test condition: 3.3Vin/5Vin, Io=20A Test condition: Io=20A
Test condition: 3.3Vin/5Vin, short circuit
Vout
Vout Io
PWRGD
Io
PWRGD
Test condition: Io=0 - 20A, T1=T2=3ms, RT=FT=2.5A/us
Test condition:3.3Vin/5Vin, 1.4Vout@20A
Vout
Vout
Io
DH1
IL1 IL2
DL1
(c) 2004 Semtech Corp.
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SC2677B
POWER MANAGEMENT Performance (Single Output)
Test condition:3.3Vin/5Vin, 1.4Vout@20A
1.4
Vout DH2 DL2
OCP
1.2 Vout (V) 1.0 0.8 0.6 0.4 0.2 0.0 0 5 10 15 20 25 30 Load Current (A)
Vo (V)
Load C urrent vs.V to V (m ) cs+ out V
8
3.3V and 5V Input Curre nt
40 35 30 25 20 15 10 5 0 0 5 10 15 20 25 30 LoadCurrent (A )
Vcs1+ to Vout1 (mV)
7 6 Input Current (A)
V cs1+to V out1 V cs2+to V out2
5 4 3 2 1 0 0 2 4 6 8 10 12 14 16 18 20 Iin3.3 A Iin5 A
Load Current (A)
Regualation Characteristic
1.4060 1.4055
Overall System Efficiency 90
Efficiency (%)
Vout (V)
1.4050 1.4045 1.4040 1.4035 1.4030
0 5 10 15 20
85 80 75 70 0 2 4 6 8 10 12 14 16 18 20 Io
Vout V
Load Current (A)
(c) 2004 Semtech Corp.
Load Current (A )
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SC2677B
POWER MANAGEMENT Outline Drawing - TSSOP-24
A e N 2X E/2 E1 PIN 1 INDICATOR ccc C 2X N/2 TIPS 123 e/2 B E D
DIM
A A1 A2 b c D E1 E e L L1 N 01 aaa bbb ccc
DIMENSIONS MILLIMETERS INCHES MIN NOM MAX MIN NOM MAX
.047 .002 .006 .031 .042 .007 .012 .003 .007 .303 .307 .311 .169 .173 .177 .252 BSC .026 BSC .018 .024 .030 (.039) 24 0 8 .004 .004 .008 1.20 0.05 0.15 0.80 1.05 0.19 0.30 0.09 0.20 7.70 7.80 7.90 4.30 4.40 4.50 6.40 BSC 0.65 BSC 0.45 0.60 0.75 (1.0) 24 0 8 0.10 0.10 0.20
aaa C SEATING PLANE
D A2 A H GAGE PLANE 0.25 (L1) SEE DETAIL L c
C bxN bbb C
A1 A-B D
01
SIDE VIEW
A
DETAIL
A
NOTES: 1. 2. 3. 4. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). DATUMS -AAND -BTO BE DETERMINED AT DATUM PLANE -H-
DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. REFERENCE JEDEC STD MO-153, VARIATION AD.
Land Pattern - TSSOP-24
X
DIM
(C) G Z C G P X Y Z
DIMENSIONS INCHES MILLIMETERS
(.222) .161 .026 .016 .061 .283 (5.65) 4.10 0.65 0.40 1.55 7.20
Y P
NOTES: 1.
THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET.
Contact Information
Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805)498-2111 FAX (805)498-3804
(c) 2004 Semtech Corp.
18
www.semtech.com
SC2677B
POWER MANAGEMENT Outline Drawing - TSSOP-24 EDP
A e N D
DIM
2X E/2 E1 PIN 1 INDICATOR ccc C 2X N/2 TIPS 123 e/2 B E
A A1 A2 b c D E1 E F H e L L1 N 01 aaa bbb ccc
DIMENSIONS INCHES MILLIMETERS MIN NOM MAX MIN NOM MAX
.047 .002 .006 .031 .042 .007 .012 .003 .007 .303 .307 .311 .169 .173 .177 .252 BSC .211 .217 .221 .118 .112 .122 .026 BSC .024 .018 .030 (.039) 24 0 8 .004 .004 .008 1.20 0.15 0.05 1.05 0.80 0.19 0.30 0.09 0.20 7.70 7.80 7.90 4.30 4.40 4.50 6.40 BSC 5.37 5.52 5.62 2.85 3.00 3.10 0.65 BSC 0.45 0.60 0.75 (1.0) 24 0 8 0.10 0.10 0.20
aaa SEATING PLANE
C
D A2 A
C bxN bbb C
A1 A-B D
SIDE VIEW
SEE DETAIL
A
H BOTTOM VIEW GAGE PLANE 0.25 (L1) F
OTES: 1. 2. 3. 4. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). DATUMS -AAND -BTO BE DETERMINED AT DATUM PLANE -H-
c
H
L
01
DETAIL
A
DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. REFERENCE JEDEC STD MO-153, VARIATION AD.
Land Pattern - TSSOP-24 EDP
F X
DIM
C F G H P X Y Z
DIMENSIONS INCHES MILLIMETERS
(.222) .225 .161 .126 .026 .016 .061 .283 (5.65) 5.72 4.10 3.20 0.65 0.40 1.55 7.20
(C)
H
G
Z
Y P
NOTES: 1.
THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET.
Contact Information
Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805)498-2111 FAX (805)498-3804
(c) 2004 Semtech Corp.
19
www.semtech.com


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